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| 71608hkim no. a1130-1/21 STK672-640A-E overview the STK672-640A-E is a hybrid ic for use as a unipolar, 2-phase stepping motor driver with pwm current control. applications ? office photocopiers, printers, etc. features ? built-in overcurrent detection function (output current off). ? built-in overheat detection function (output current off). ? if either over-current or overheat detection function is activated, the fault signal (active low) is output. ? built-in power on reset function. ? the motor speed is controlled by the frequency of an external clock signal. ? 2 phase or 1-2 phase excitation switching function. ? using either or both edges of the clock signal switching function. ? phase is maintained even when the excitation mode is switched. ? rotational direction switching function. ? supports schmitt input for 2.5v high level input. ? incorporating a current detection resistor (0.089 : resistor tolerance 2%), motor current can be set using two external resistors. ? the enable pin can be used to cut output current while maintaining the excitation mode. ? with a wide current setting range, power consumption can be reduced during standby. ? no motor sound is generated during hold mode due to external excitation current control. ordering number : en*a1130 thick-film hybrid ic 2-phase stepping motor driver specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
STK672-640A-E no. a1130-2/21 specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 52 v maximum supply voltage 2 v dd max no signal -0.3 to +6.0 v input voltage v in max logic input pins -0.3 to +6.0 v output current 1 i op max 10 a, 1 pulse (resistance load) 20 a output current 2 i oh max v dd =5v, clock 200hz 4 a output current 3 i of max pin16 output current 10 ma allowable power dissipation 1 pdmf max with an arbitrarily large heat sink. per mosfet 8.3 w allowable power dissipation 2 pdpk max no heat sink 3.1 w operating substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta=25 c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 10 to 42 v operating supply voltage 2 v dd with signals applied 5 5% v input high voltage v ih pins 10, 12, 13, 14, 15, 17 2.5 to v dd v input low voltage v il pins 10, 12, 13, 14, 15, 17 0 to 0.8 v output current 1 i oh 1 tc=105 c, clock 200hz, continuous operation, duty=100% 3.0 a output current 2 i oh 2 tc=80 c, clock 200hz, continuous operation, duty=100%, see the motor current (i oh ) derating curve 3.3 a clock frequency f cl minimum pulse width: at least 10 s 0 to 50 khz phase driver withstand voltage v dss i d =1ma (tc=25 c) 100min v recommended operating substrate temperature tc no condensation 0 to 105 c recommended vref range vref tc=105 c 0.14 to 1.31 v refer to the graph for each conduction-period toleranc e range for the output current and brake current. electrical characteristics at tc=25 c, v cc =24v, v dd =5.0v parameter symbol conditions min typ max unit v dd supply current i cco pin 9 current clock=gnd 4.4 8 ma output average current ioave r/l=1 /0.62mh in each phase 0.519 0.625 0.731 a fet diode forward voltage vdf if=1a (r l =23 ) 0.83 1.5 v output saturation voltage vsat r l =23 0.20 0.33 v input high voltage v ih pins 10, 12, 13, 14, 15, 17 2.5 v input low voltage v il pins 10, 12, 13, 14, 15, 17 0.8 v fault low output voltage v olf pin 16 (i o =5ma) 0.25 0.5 v 5v level fault leakage current i ilf pin 16=5v 10 a 5v level input current i ilh pins 10, 12, 13, 14, 15, 17=5v 50 75 a gnd level input current i ill pins 10, 12, 13, 14, 15, 17=gnd 10 a vref input bias current i ib pin 19=1.0v 10 15 a pwm frequency fc 29 45 61 khz overheat detection temperature tsd design guarantee 144 c *ioave values are for when the lead frame of the product is soldered to the mounting substrate. notes: a fixed-voltage power supply must be used. STK672-640A-E no. a1130-3/21 package dimensions unit:mm (typ) derating curve of motor current, i oh, vs. STK672-640A-E operating substrate temperature, tc notes ? the current range given above represents conditions wh en output voltage is not in the avalanche state. ? if the output voltage is in the avalanche state, see the allowable avalanche energy for stk672-6** series hybrid ics given in a separate document. ? the operating substrate temperature, tc, given abov e is measured while the motor is operating. ? because tc varies depending on the am bient temperature, ta, the value of i oh , and the continuous or intermittent operation of i oh , always verify this value using an actual set. 29.2 25.6 (20.47) (5.0) (12.9) (5.6) 1.0 4.2 8.2 (20.4) 0.52 0.4 4.5 119 7.2 14.5 11.0 (5.0) (r1.7) (3.5) 2.0 14.5 14.4 18 1.0=18.0 4.5 0.5 0 080 20 40 60 100 70 10 30 50 90 110 itf02588 3.0 2.0 4.0 2.5 3.5 1.5 1.0 i oh - tc operating substrate temperature, tc- c motor current, i oh - a 200hz 2-phase excitation hold mode STK672-640A-E no. a1130-4/21 block diagram sample application circuit phase excitation signal generator excitation mode selection phase advance counter fao ai bi v ss power-on reset current control chopper circuit overcurrent detection fault signal (open drain) overheating detection v dd =5v mode1 clock cwb enable fault v dd vref vref f1 f2 f3 f4 p.g2 fab fbo fbb n.c mode2 resetb r1 r2 n.c a p.g1 s.g v ss vref/4.9 v ss 100k amplifier ab b bb n.c latch circuit 2 6 1 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 latch circuit stk672-640 a -e + 9 12 10 17 13 15 14 16 19 18 6 2 5 4 1 3 v dd (5v) clock mode1 mode2 cwb enable resetb fault a ab b bb vref r01 r03 r02 s.g p.g1 p.g2 p.gnd v cc 24v c01 at least 100 f 2 phase stepping motor driver STK672-640A-E no. a1130-5/21 precautions [gnd wiring] ? to reduce noise on the 5v system, be sure to place the gnd of c01 in the circuit given above as close as possible to pin 2 and pin 6 of the hybrid ic. also, to achieve accurate current settings, be sure to connect vref gnd to pin 18 (s.g) used to set the current and to the poi nt where p.g1 and p.g2 share a connection. [input pins] ? if v dd is being applied, use care that each input pin does not apply a negative voltage less than -0.3v to s.g, pin 18, and do not apply a voltage greater than or equal to v dd voltage. ? do not wire by connecting the circuit pattern on the p.c.b side to pins 7, 8, or 11 on the n.c. shown in the internal block diagram. ? apply 2.5v high level input to pins 10, 12, 13, 14, 15, and 17. ? since the input pins do not have built-in pull-up resistors, wh en the open-collector type pins 10, 12, 13, 14, 15, and 17 are used as inputs, a 1 to 20k pull-up resistor (to v dd ) must be used. at this time, use a device for the open collector driver that has output current specifications that pull the voltage down to less than 0.8v at low level (less than 0.8v at low level when i ol =5ma). [current setting vref] ? considering the specifications of the vref input bias current, i ib , a value of 1k or less is recommended for r02. if the motor current is temporarily reduced, the circuit given below (stk672-630a-e: i oh >0.2a, STK672-640A-E: i oh >0.3a) is recommended. ? motor current peak value i oh setting i oh =(vref 4.9) rs the value of 4.9 in equation above represents the vref voltage as divided by a circuit inside the control ic. vref=(r02 (r01+r02)) 5v(or 3.3v) rs is an internal current detection resistor value of the hybrid ic. rs=0.141 when using the stk672-630a-e rs=0.089 when using the STK672-640A-E 5v r01 r02 r3 5v r01 r02 r3 vref vref i oh 0 STK672-640A-E no. a1130-6/21 [smoke emission precuations] if pin 18 (s.g terminal) is attached to the pcb without using solder, overcurrent may flow into the mosfet at v cc on (24v on), causing the stk672 -630a-e, stk672-640 a-e to emit smoke because 5v circuits cannot be controlled. in addition, as long as one of the output pins, 1, 3, 4, or 5, is open, inductance energy stored in the motor results in electrical stress on the driver, possibly resulting in the emission of smoke. input pin functions pin name pin no. function input conditions when operating clock 12 reference clock for motor phase current switching operates on the rising edge of the signal (mode2=h) mode1 10 low: 2-phase excitation high: 1-2 phase excitation mode2 17 excitation mode selection high: rising edge low: rising and falling edge cwb 13 motor direction switching low: cw (forward) high: ccw (reverse) resetb 14 system reset initial state of a and bb phase excitation in the timing charts is set by switching from low to high. a reset is applied by a low level enable 15 the a, ab, b, and bb outputs are turned off, and after operation is restored by returning the enable pin to the high level, operation continues with the same excitation timing as before the low-level input. the a, ab, b, and bb outputs are turned off by a low- level input. output pin functions pin name pin no. function input conditions when operating fault 16 monitor pin used when over-current detection or overheat detection function is activated. low level is output when detected. note: see the timing chart for the concrete details on circuit operation. STK672-640A-E no. a1130-7/21 timing charts 2-phase excitation 1-2 phase excitation power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb STK672-640A-E no. a1130-8/21 1-2 phase excitation (cwb) 2 phase excitation switch to 1-2 phase excitation power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb STK672-640A-E no. a1130-9/21 1-2 phase excitation (enable) 1-2 phase excitation (hold operation results during fixed clock) power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb hold operation power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb STK672-640A-E no. a1130-10/21 2 phase excitation (mode 2) 1-2 phase excitation (mode 2) power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb STK672-640A-E no. a1130-11/21 usage notes 1. stk672-630a-e, STK672-640A-E input signal functions and timing [enable, clock and power on reset, resetb (in put signal timing when power is first applied)] the control ic of the driver is equipped with a power on reset function capable of initializing internal ic operations when power is supplied. a 4v typ settin g is used for power on reset. because the specification for the mosfet gate voltage is 5v 5%, conduction of current to output at the time of power on reset adds electromotive stress to the mosfet due to lack of gate voltage. to prevent electromotive stress, be sure to set enable=low while v dd , which is outside the operating supply voltage, is less than 4.75v. in addition, if the resetb terminal is used to in itialize output timing, be sure to allow at least 10 s until clock input. enable, clock, and res etb signals input timing [clock (phase switching clock)] ? input frequency: dc to 50khz ? minimum pulse width: 10 s ? mode2=1(high) signals are read on the rising edge. ? mode2=0(low) signals are read on the rising and falling edges. [cwb (motor direction setting)] the direction of rotation is switched by setting cwb to 1 (high) or 0 (low). see the timing charts for details on the operation of the outputs. note: the state of the cwb input must not be changed during the 6.25 s period before and after the rising edge of the clock input. [enable (forcible on/off control of the a, ab, b, and bb outputs, and hybrid ic internal operation)] enable=1: normal operation enable=0: outputs a, ab, b, an d bb forced to the off state. if, during the state where clock signal input is provid ed, the enable pin is set to 0 and then is later restored to the 1 state, the ic will resume operatio n with the excitation timing continued from before the point enable was set to 0. if sudden stop is applied to the clock signal used for motor rotation, the motor axis may advance beyond the theoretical position due to inertia. to stop at the theore tical position, the slow down setting for gradually slowing the clock cycle is required. 4v typ 3.8v typ at least 10 STK672-640A-E no. a1130-12/21 [mode1 and mode2 (excitation mode selection)] mode1=0: 2-phase excitation mode2=1: rising edge of clock mode1=1: 1-2 phase excitation mode2=0: rising and falling edges of clock see the timing charts for details on output operation in these modes. note: the state of the mode input must not be changed during the 5 s period before and after the rising edge of the clock input. [configuration of each input pin] STK672-640A-E no. a1130-13/21 2. overcurrent detection and overheat detection functions of the stk672-630a-e and STK672-640A-E each detection function operates using a latch system and turns output off. because a reset signal is required to restore output operations, once the power supply, v dd , is turned off, you must eith er again apply power on reset with v dd on or apply a resetb=high low high signal. [overcurrent detection] this hybrid ic is equipped with a function for detecting over current that arises when the motor burns out or when there is a short between the motor terminals. overcurrent detection occurs at 3.5a typ with the stk672-630a-e and at 5.5a typ for the STK672-640A-E. overcurrent detection begins after an interval of no detection (a dead time of 5.5 s typ) during the initial ringing part during pwm operations. the no detection interval is a peri od of time where overcurrent is not detected even if the current exceeds i oh . [overheat detection] rather than directly detecting the temperature of the semi conductor device, overheat dete ction detects the temperature of the aluminum substrate (144 c typ). within the allowed operating range reco mmended in the specification manual, if a heat sink attached for the purpose of reducing the operating substrate temp erature, tc, comes loose, the semic onductor can operate without breaking. however, we cannot guarantee operations without breaking in the case of operations other than those recommended, such as operations at a current exceeding i oh max that occurs before over current detectio n is activated. 5.5 , s typ) mosfet all off over-current detection operation when motor pins are shorted current when motor terminals are shorted STK672-640A-E no. a1130-14/21 3. calculating STK672-640A-E hic internal power loss the average internal power loss in each excitation mode of the STK672-640A-E can be ca lculated from the following formulas. each excitation mode 2-phase excitation mode 2pdavex=(vsat+vdf) 0.5 clock i oh t2+0.5 clock i oh (vsat t1+vdf t3) 1-2 phase excitation mode 1-2pdavex=(vsat+vdf) 0.25 clock i oh t2+0.25 clock i oh (vsat t1+vdf t3) motor hold mode holdpdavex= (vsat+vdf) i oh vsat: combined voltage represented by the ron voltage drop+shunt resistor vdf: combined voltage represented by the mosfet body diode+shunt resistor clock: input clock (clock pin signal frequency) t1, t2, and t3 represent the waveforms shown in the figure below. t1: time required for the winding cu rrent to reach the set current (i oh ) t2: time in the constant current control (pwm) region t3: time from end of phase input signal until inverse current regeneration is complete motor com current waveform model t1= (-l/(r+0.20)) in (1-((r+0.20)/v cc ) i oh ) t3= (-l/r) in ((v cc +0.20)/(i oh r+v cc +0.20)) v cc : motor supply voltage (v) l: motor inductance (h) r: motor winding resistance ( ) i oh : motor set output current crest value (a) relationship of clock, t1, t2, and t3 in each excitation mode 2-phase excitation mode: t2= (2/clock) - (t1+t3) 1-2 phase excitation mode: t2= (3/clock) -t1 for vsat and vdf, be sure to substitute values from the graphs of vsat vs. i oh and vdf vs. i oh while the set current value is i oh . then, determine whether a heat sink is re quired by comparing with the graph of tc vs. pd based on the average hic power loss calculated. when designing a heat sink, refer to the section ?thermal design? found on the next page. the average hic power loss, pdav, described above does not have the avalanche?s loss. to include the avalanche?s loss, be sure to add equation (2), ?stk672-6** allowable avalanche energy valu e? to pdav above. when using this ic without a fin always check for temperature increases in the set, because the hic substrate temper ature, tc, varies due to effects of convection around the hic. i oh 0a t1 t2 t3 STK672-640A-E no. a1130-15/21 STK672-640A-E output saturation voltage, vsat - output current, i oh STK672-640A-E forward voltage, vdf -output current, i oh substrate temperature rise, tc (no heat sink) - internal average power dissipation, pdav 0 0.5 1.0 1.5 2.5 4.5 3.5 3.0 2.0 4.0 0.4 0.2 0 itf02589 1.0 0.8 0.6 2 5 c t c = 1 05 c vsat - i oh output current, i oh - a output saturation voltage, vsat - v 0 0.5 1.0 1.5 4.5 3.5 2.5 3.0 2.0 4.0 0.4 0.2 0 itf02590 1.4 1.0 1.2 0.8 0.6 t c = 2 5 c 1 0 5 c vdf- i oh output current, i oh - a forward voltage, vdf - v 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 itf02551 50 70 60 40 30 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c STK672-640A-E no. a1130-16/21 4. STK672-640A-E allowabl e avalanche energy value (1) allowable range in avalanche mode when driving a 2-phase stepping motor with constant current chopping using an stk672-6** series hybrid ic, the waveforms shown in figure 1 belo w result for the output current, i d , and voltage, v ds . figure 1 output current, i d , and voltage, v ds , waveforms 1 of the stk672-6** series when driving a 2-phase stepping motor with constant current chopping when operations of the mosfet built into stk672-6** seri es ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (1). eavl1=v dss iavl 0.5 tavl ------------------------------------------- (1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (1) is a constant required to convert the iavl triangle wave to a square wave. during stk672-6** series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy, eavl, is therefore represented by equation (2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (1). pavl=v dss iavl 0.5 tavl fc ------------------------------------------- (2) fc: hz units (fc is set to the pwm frequency of 50khz.) for v dss , iavl, and tavl, be sure to actually operate th e stk672-6** series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=1a, tavl=0.2 s when using a stk672-640a -e driver, the result is: pavl=110 1 0.5 0.2 10 -6 50 10 3 =0.55w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 3. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calculating equation (2) falls within the allowable range for avalanche operations. v dss : voltage during avalanche operations i oh : motor current peak value iavl: current during avalanche operations tavl: time of avalanche operations v ds i d itf02557 STK672-640A-E no. a1130-17/21 (2) i d and v dss operating waveforms in non-avalanche mode although the waveforms during avalanche mode are given in figure 1, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness caused by the circuit pattern of the p.c. board and motor. ? increases in v dss , tavl, and iavl in figure 1 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 1 become waveforms without avalanche as shown in figure 2. under operations shown in figure 2, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 3. figure 2 output current, i d , and voltage, v ds , waveforms 2 of the stk672-6** series when driving a 2-phase stepping motor with constant current chopping figure 3 allowable loss range, pavl-i oh during STK672-640A-E avalanche operations note: the operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. because it is possible to apply 3w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. 0 0.5 1.0 1.5 2.5 2.0 3.5 3.0 1.0 0.5 0 itf02591 5.0 3.5 4.5 2.5 3.0 4.0 2.0 1.5 t c = 8 0 c 1 0 5 c pavl - i oh motor phase current, i oh - a average power loss in the avalanche state, pavl- w i oh : motor current peak value v ds i d itf02558 STK672-640A-E no. a1130-18/21 5. thermal design [operating range in which a heat sink is not used] use of a heat sink to lower the operating substrate temperat ure of the hic (hybrid ic) is effective in increasing the quality of the hic. the size of heat sink for the hic varies depending on the magnitude of the average power loss, pdav, within the hic. the value of pdav increases as the output current increases. to calculate pdav, refer to ?calculating internal hic loss for the stk672-630a-e, STK672-640A-E? in the specification document. calculate the internal hic loss, pdav, assuming repeat operation such as shown in figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, figure 1 motor current timing t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation pdav can be cal culated from the following formula. pdav= (t1 p1+t2 p2+t3 0) to ---------------------------- (i) (here, p1 is the pdav for i o 1 and p2 is the pdav for i o 2) if the value calculated using equation (i) is 1.5w or less, and the ambient temperature, ta, is 60 c or less, there is no need to attach a heat sink. refer to figure 2 for operating substrate temperature data when no heat sink is used. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if pdav in creases, the resulting size can be found using the value of c-a in equation (ii) below and the graph depicted in figure 3. c-a= (tc max-ta) pdav ---------------------------- (ii) tc max: maximum operating substrate temperature =105 c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 c or less. the average hic power loss, pdav, described above represents the power loss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (2), ?allowable stk672-6** avalanche energy value?, to pdav. i o 1 i o 2 -i o 1 0a t1 t2 t3 t0 motor phase current (sink side) STK672-640A-E no. a1130-19/21 figure 2 substrat e temperature rise, tc (no heat sink) - internal average power dissipation, pdav figure 3 heat sink area (board thickness: 2mm) - c-a 6. mitigated curve of package power loss, pdpk, vs. ambient temperature, ta package power loss, pdpk, refers to the average internal power loss, pdav, allowable without a heat sink. the figure below represents the allowable power loss, pd pk, vs. fluctuations in the ambient temperature, ta. power loss of up to 3.1w is allowable at ta=25 c, and of up to 1.75w at ta=60 c. allowable power dissipation, pdpk(no heat sink) - ambient temperature, ta 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 itf02553 50 70 60 40 30 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c 2 1.0 2 100 7 10 35 2 7 35 1000 itf02554 5 100 3 10 7 2 5 3 7 c-a - s heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w w i t h n o s u r f a c e f i n i s h w i t h a f l a t b l a c k s u r f a c e f i n i s h 1.0 0.5 0 080 20 40 60 100 120 itf02511 2.5 3.0 3.5 2.0 1.5 pdpk - ta ambient temperature,ta - c allowable power dissipation, pdpk - w STK672-640A-E no. a1130-20/21 7. example of stepping motor driver out put current path (1-2 phase excitation) clock i o a i o ab phase a output current phase ab output current pwm operations when pwm operations of i o a are off, for i o ab, negative current flows through the parasitic diode, f2. when pwm operations of i o ab are off, for i o a, negative current flows through the parasitic diode, f1. + 24v 2-phase stepping motor p.gnd c02 at least 100 v 100k amp ab b bb n.c vref STK672-640A-E no. a1130-21/21 ps this catalog provides information as of july, 2 008. specifications and info rmation herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. |
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